1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a non-volatile memory device and a fabricating method thereof.
2. Description of the Related Art
A non-volatile memory device such as an electrically-erasable-programmable read-only-memory (EEPROM) is a read only memory (ROM) that can be erased and reprogrammed through the application of electrical voltage. Typical examples of the EEPROM are a flash memory device and a floating gate tunnel oxide (FLOTOX) memory device. FLOTOX memory device employ memory cells comprising two transistors, that is, a memory transistor and a selection transistor. A cell array of the flash memory device may be classified into a NAND-type cell array and NOR-type cell array. In the NAND-type cell array, cell strings are arranged in parallel in a cell array region. The cell strings comprise a plurality of memory cells, which are connected in series. The cell strings of the NAND-type cell array include the selection transistor on both ends thereof. While the selection transistor of the FLOTOX memory cell selects the memory cell, the selection transistor of the NAND-type flash memory cell selects the string cells.
Referring to FIG. 1, in the conventional NAND-type flash memory device, a device isolation layer 2 is formed on a semiconductor substrate 10. The device isolation layer 2 defines a plurality of active regions 4 in the substrate 10. A string selection line (SSL), a ground selection line (GSL) and a plurality of word lines (WL) intersecting the active regions 4 are arranged. The string selection line (SSL), the ground selection line (GSL) and a plurality of word lines (WL) constitute a memory cell unit (i.e., Block). The NAND-type cell array comprises a plurality of the memory cell units. Adjoining memory cell units are arranged symmetrically. Common source line (CSL) is arranged between the ground selection lines (GSL). The common source line (CSL) is electrically connected to the active regions 4. A bit line plug 44 is arranged on each active region 4 between the string selection lines (SSL).
The word lines (WL) comprise a control gate electrode 49 and a floating gate 32. The control gate electrode 49 extends across the active regions 4, and the floating gate 32 interposed between the control gate electrode 49 and each active region 4. The ground selection line (GSL) and the string selection line (SSL) comprise a bottom gate pattern 24 and a top gate pattern 30, which are sequentially stacked. The word line (WL) includes an inter-gate dielectric. The inter-gate dielectric electrically insulates the control gate electrode 49 and the floating gate 32. To the contrary, the top gate pattern 30 and the bottom gate pattern 24 are electrically connected. The method for electrically connecting the top gate pattern 30 and the bottom gate pattern 24 is disclosed in U.S. Pat. Nos. 4,780,431 and 6,221,717, the contents of which are incorporated herein by reference.
Referring to FIG. 2, the device isolation layer 4 is formed on the semiconductor substrate 10 to define the active regions 2. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate 10. The first conductive layer is patterned to form a first conductive pattern 14. The inter-gate dielectric 16 and a mask layer 18 are sequentially formed on the semiconductor substrate 10 including the first conductive pattern 14. The mask layer 18 and the inter-gate dielectric 16 are sequentially patterned to form an opening 20 exposing the first conductive pattern 14. Although not shown, the opening 20 crosses over the active regions 2. The opening 20 is positioned in the center of region (S) where a selection line (SL) is to be formed (FIG. 3).
Referring to FIG. 3, a second conductive layer is formed on the mask conductive layer 18 including the opening 20. The second conductive layer, the mask conductive layer 18, the inter-gate dielectric 16 and the first conductive pattern 14 are sequentially patterned to form the word line (WL) and the selection line (SL). The word line (WL) comprises the floating gate 34, a first inter-gate dielectric 36, a first mask conductive layer 38 and the control gate electrode 40. The selection line (SL) comprises the bottom gate pattern 24, a second inter-gate dielectric 26, a second mask conductive layer 28 and a top gate pattern 30. While the floating gate 34 and the control gate electrode 40 are electrically insulated, the bottom gate pattern 24 and the top gate pattern 30 are electrically connected to each other through the opening 20. The width of the opening 20 may be half of the width of the selection line (L). In this case, a permitted misalignment of the opening 20 and the selection line (SL) is L/4.
Referring to FIG. 4, when the opening 20 or the selection line (SL) misaligns, a portion 46 of the opening 20 is placed outside of a selection line region (S).
Referring to FIG. 5, the second conductive layer is formed. Then, the second conductive layer and the mask conductive layer are patterned using the inter-gate dielectric as an etch stop layer to form the control gate electrode 40, the top gate pattern 30, and the first and second mask conductive layers 38 and 28. In this case, the first conductive pattern 14 is removed to expose the gate insulation layer 12 in the opening region 46 placed outside of the selection line region (S).
Referring to FIG. 6, the inter-gate dielectric 16 and the first conductive pattern 14 are patterned to form the floating gate 34, the bottom gate pattern 24, and the first and second inter-gate dielectrics 36 and 26. In this case, the substrate of the opening region 20 can be damaged by etching. Worse yet, a notch 48 can be formed adjacent the selection line (SL).